(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of an improved buried contact without a trench in the fabrication of integrated circuits.
(2) Description of the Prior Art
A typical buried contact is formed by depositing a doped layer of polysilicon over and on the planned buried contact regions and heating the structure. The buried contact regions are doped by outdiffusion of dopants from the doped polysilicon layer into the silicon substrate. The doped polysilicon layer is allowed to remain on the buried contact regions as their contacts. If there is misalignment of the mask during etching of the polysilicon, a portion of the semiconductor substrate within the buried contact area will be exposed. During polysilicon overetching, a buried contact trench will be etched. This interrupts the transistor current flow path causing device failure.
Silicon Processing for the VLSI Era, Vol. 2 by Stanley Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 160-162 describes the use of buried contacts and local interconnections. U.S. Pat. No. 5,350,712 to Shibata teaches the use of an additional metal width around a metal line to overcome mask misalignment problems causing etching of the semiconductor substrate. Co-pending U.S. patent application Ser. No. 08/488,764, now U.S. Pat. No. 5,525,552 to J. M. Huang, filed on Jun. 8, 1995, teaches the use of a low dielectric constant spacer to provide better immunity of the buried contact trench. Co-pending U.S. patent application Ser. No. 08/503,173, now U.S. Pat. No. 5,607,881 also to J. M. Huang, filed on Jul. 17, 1995, teaches linking the buried contact junction and the source junction by an extra high dosage N+ implant to overcome the disadvantages of a buried contact trench. Allowed U.S. patent application Ser. No. 08/405,719, now U.S. Pat. No. 5,494,848 to H. W. Chin, filed on Mar. 17, 1995, teaches the use of a reverse tone oversized buried contact mask to prevent formation of a buried contact trench. Co-pending U.S. patent application Ser. No. 08/668,801 to C. Y. Shi et al teaches the use of TEOS sidewall spacers to prevent the formation of a buried contact trench in DRAM technology.